//! RK3588 GPIO register definitions

/// GPIO register offsets (based on RK3588 TRM Chapter 20)
pub mod offset {
    // Data registers (write-mask capable)
    pub const SWPORT_DR_L: usize = 0x0000; // Data register low bits (pins 0-15)
    pub const SWPORT_DR_H: usize = 0x0004; // Data register high bits (pins 16-31)

    // Direction registers (write-mask capable)
    pub const SWPORT_DDR_L: usize = 0x0008; // Direction register low bits (pins 0-15)
    pub const SWPORT_DDR_H: usize = 0x000C; // Direction register high bits (pins 16-31)

    // Interrupt enable registers (write-mask capable)
    pub const INT_EN_L: usize = 0x0010; // Interrupt enable low bits
    pub const INT_EN_H: usize = 0x0014; // Interrupt enable high bits

    // Interrupt mask registers (write-mask capable)
    pub const INT_MASK_L: usize = 0x0018; // Interrupt mask low bits
    pub const INT_MASK_H: usize = 0x001C; // Interrupt mask high bits

    // Interrupt type registers (write-mask capable)
    pub const INT_TYPE_L: usize = 0x0020; // Interrupt type low bits (0 = level, 1 = edge)
    pub const INT_TYPE_H: usize = 0x0024; // Interrupt type high bits

    // Interrupt polarity registers (write-mask capable)
    pub const INT_POLARITY_L: usize = 0x0028; // Interrupt polarity low bits (0 = low/falling, 1 = high/rising)
    pub const INT_POLARITY_H: usize = 0x002C; // Interrupt polarity high bits

    // Double-edge interrupt registers (write-mask capable)
    pub const INT_BOTHEDGE_L: usize = 0x0030; // Double-edge interrupt low bits
    pub const INT_BOTHEDGE_H: usize = 0x0034; // Double-edge interrupt high bits

    // Debounce registers (write-mask capable)
    pub const DEBOUNCE_L: usize = 0x0038; // Debounce low bits
    pub const DEBOUNCE_H: usize = 0x003C; // Debounce high bits

    // Debounce clock divider registers (write-mask capable)
    pub const DBCLK_DIV_EN_L: usize = 0x0040; // Divider enable low bits
    pub const DBCLK_DIV_EN_H: usize = 0x0044; // Divider enable high bits
    pub const DBCLK_DIV_CON: usize = 0x0048; // Divider control (24-bit)

    // Interrupt status registers (read-only, 32-bit)
    pub const INT_STATUS: usize = 0x0050; // Interrupt status
    pub const INT_RAWSTATUS: usize = 0x0058; // Raw interrupt status

    // Interrupt clear registers (write-mask, self-clearing)
    pub const PORT_EOI_L: usize = 0x0060; // Interrupt clear low bits
    pub const PORT_EOI_H: usize = 0x0064; // Interrupt clear high bits

    // External port registers (read-only, 32-bit)
    pub const EXT_PORT: usize = 0x0070; // External port (reads all 32 pins)

    // Version and control registers
    pub const VER_ID: usize = 0x0078; // Version ID
    pub const REG_GROUP_L: usize = 0x0100; // GPIO group control low bits (dual OS support)
    pub const REG_GROUP_H: usize = 0x0104; // GPIO group control high bits
    pub const VIRTUAL_EN: usize = 0x0108; // Virtual mode enable
}

/// GPIO direction
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Direction {
    Input  = 0,
    Output = 1,
}

/// GPIO level
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Level {
    Low  = 0,
    High = 1,
}

impl From<bool> for Level {
    fn from(value: bool) -> Self {
        if value { Level::High } else { Level::Low }
    }
}

impl From<Level> for bool {
    fn from(level: Level) -> Self {
        level == Level::High
    }
}

/// Interrupt trigger type
#[derive(Debug, Clone, Copy)]
pub enum TriggerType {
    LevelLow,    // Trigger on low level
    LevelHigh,   // Trigger on high level
    EdgeFalling, // Trigger on falling edge
    EdgeRising,  // Trigger on rising edge
    EdgeBoth,    // Trigger on both edges (RK3588 specific)
}
